Algorithm for Power Minimization in Scan Sequential Circuits

1 ALGORITHM FOR POWER MINIMIZATION IN SCAN SEQUENTIAL CIRCUITS 1Harpreet Singh, 2Dr. Sukhwinder Singh 1M.E. (VLSI DESIGN), PEC University of Technology, Chandigarh. 2Professor, PEC University of Technology, Chandigarh Email: [email protected] . Abstract— The paper describes a An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The technique increases the correlation between successive states, during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. The paper presents a new algorithm which determines the primary input change time, such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application.